1. Technical Field
This disclosure relates generally to active substrates using organic transistors, and more particularly to an organic transistor active substrate, a manufacturing method thereof, and an electrophoretic display using the organic transistor active substrate that can be manufactured by simple methods at low cost.
2. Description of the Related Art
Conventionally, the following matrix type displays are known: passive type displays and active type displays. A passive type display is driven by a scanning electrode and a data electrode that are mutually orthogonal. An active type display selects pixels to be lit by using a switching element such as a transistor and a memory element.
Examples of active type displays are disclosed in Japanese Laid-Open Patent Application No. 2003-255857 “Organic EL Display” (Patent Document 1), Japanese Laid-Open Patent Application No. 2003-318196 “Active element and display device with the same” (Patent Document 2), Japanese Laid-Open Patent Application No. 2004-241527 “Organic active element and display element having the same” (Patent Document 3), and Japanese Laid-Open Patent Application No. 2005-64122 “Ink and method for forming organic semiconductor pattern, electronic element, and electronic element array” (Patent Document 4). An active type display has a structure driven by a simple matrix, and an active element (switching element) is added to each pixel, so that a target pixel can be turned on/off. Accordingly, active type displays can be used for displaying videos when high image quality and fast response speed are required.
In the technology disclosed in Japanese Laid-Open Patent Application No. 2003-255857 (Patent Document 1), each pixel included in a matrix array formed on a substrate includes at least one organic EL (Electro Luminescence) element which is driven by two or more organic thin-film transistors (TFTs). Each organic TFT includes a gate electrode, a gate insulating film, an organic semiconductor layer coating the gate insulating film, a source electrode, and a drain electrode. The gate insulating film serves as an active substrate for an organic EL display, which includes a metal oxide film that is formed by anodically oxidizing the surface of the gate electrode. Accordingly, organic TFTs of low threshold voltage and low operating voltage can be formed at a low process temperature.
Organic semiconductor active elements (transistors) and electrophoretic display devices using the active elements are disclosed in Japanese Laid-Open Patent Application No. 2003-318196 (Patent Document 2) and Japanese Laid-Open Patent Application No. 2004-241527 (Patent Document 3).
Japanese Laid-Open Patent Application No. 2005-64122 (Patent Document 4) discloses ink that is useful for forming organic semiconductor patterns, and an electronic element and an electronic element array in which electrodes are formed by an inkjet printing method employing the aforementioned ink.
Patent Document 1: Japanese Laid-Open Patent Application No. 2003-255857
Patent Document 2: Japanese Laid-Open Patent Application No. 2003-318196
Patent Document 3: Japanese Laid-Open Patent Application No. 2004-241527
Patent Document 4: Japanese Laid-Open Patent Application No. 2005-64122
As described in the above conventional technologies, there have been attempts to manufacture display panels by disposing transistors made of organic semiconductor materials on arrays to form active substrates, and laminating the active substrates with display elements. FIG. 4 is a schematic diagram of such a display panel. As shown in FIG. 4, electrophoretic microcapsules 9 are provided between an electrode of an active substrate and a transparent electrode 10. A supporting substrate is denoted by 11.
Another example of a display panel is shown in FIG. 7. An electrophoretic dispersion liquid 13 is provided in spaces (denoted by 13), which spaces are formed by providing partition layers 12 that join the supporting substrate and the active substrate.
The active substrate is laminated with the display element as follows. As shown in FIG. 1, an organic thin-film transistor (hereinafter, “organic TFT) includes a substrate 1, a gate electrode 2, a gate insulating layer 3, source/drain electrodes 4, and an active layer 5. As shown in FIG. 2, a pixel electrode (individual electrode 8) needs to be disposed on the organic TFT via an interlayer insulating film 6. However, properties of the organic TFT may deteriorate when forming the interlayer insulating film 6 or subsequently forming a through-hole 7.
The following conditions need to be satisfied when forming the interlayer insulating film 6: (1) form the film at low temperature (when the substrate is made of plastic, the process temperature is to be equal to or less than 200° C.); (2) prevent damage (transistor performance is prevented from declining due to film formation); and (3) keep the process simple (keep costs low; vacuum film formation entails high costs in the device and large environmental effect (e.g. electricity)).
Next, conventional methods of forming the interlayer insulating film 6 and their problems are described.    a) Vacuum film formation of inorganic insulating film    a1) Plasma CVD (chemical vapor deposition) method using silane gas
not simple process, plasma damage occurs    a2) Sputtering method
not simple process, plasma damage occurs    a3) Film formation by SOG (spin on glass)
requires heat treatment at a temperature equal to or greater than 200° C.    b) Organic insulating layer    b1) Cast film formation by various insulating polymers    Among the above examples, the b) organic insulating layer is considered as preferable.
Methods of forming the interlayer insulating film 6 and their problems are described in further detail.
First, methods of forming the a) inorganic insulating film and their problems are described.
The a1) plasma CVD (chemical vapor deposition) method is performed by placing a sample in a vacuum chamber and evacuating the chamber. Silane gas serving as material gas and reactant gas that promotes oxidation reaction are injected into the chamber. A desired oxidized silicon film is obtained due to adherence/thermal decomposition reaction of the material gas on the substrate surface. The plasma CVD method assists the reaction by discharging radio frequency energy, and is therefore advantageous in film formation at low temperature. The plasma CVD method is typically performed with the substrate temperature at about 300° C.
Next, a description is given of the a2) sputtering method, which is also a type of vacuum film formation method, similar to the plasma CVD method.
In the sputtering method, an argon gas plasma is formed by discharging RF energy as mentioned above. A target material to be used for film formation is placed facing against the substrate and deposited onto the substrate by a sputtering phenomenon. The film formation can be performed in room temperature, although the film quality may depend on the temperature.
Disadvantages of the above film formation methods are as follows:    (1) Inconvenience of using a vacuum device    (2) The sample is exposed to an environment including positive charges and negative charges, which electrically damage the sample (generally referred to as plasma damage). Particularly, failures occur when forming an interlayer insulating layer on the transistor. Examples of the failures include drifting of the threshold voltage of the transistor and a decline in the insulating resistance value of the gate insulating film.
Next, problems of the a3) SOG method are described.
In a typical SOG method, a solution whose major component is tetraethoxysilane is made into a coating film by spin coating and then heat treated to obtain an oxide silicon film. Accordingly, film formation can be performed with a simple device such as a spin coating device, without requiring a vacuum device. However, in this film formation method, tetraethoxysilane is subject to hydrolytic cleavage, polycondensation, and dehydration reaction; therefore, heat treatment of 200° C. is required (heat treatment of 400° C. is required in the case of withdrawal of residual water group). Accordingly, this method cannot be employed when the substrate is made of a material such as plastic, which restricts the heat treatment temperature.
As described above, a) formation of inorganic insulating films entails various problems; therefore, organic insulating films are preferable. However, when forming organic insulating films, it is necessary to open a through-hole to obtain conductivity between one of the pair of electrodes of the transistor and the pixel electrode.
Generally, the through-hole is opened by photolithographic etching. However, when forming an organic insulating film, there is a problem in that an organic solvent included in photoresist elutes the base insulating film. The organic solvent used for removing the photoresist after the etching process also elutes the base insulating film.
When the etching is done by a dry process, plasma damage is incurred by the TFT. Specifically, the sample is disposed on the side of a ground electrode in a vacuum chamber in which RF plasma can be discharged, a reactant gas including a fluorine compound is injected into the chamber, and plasma is generated. On the ground side, the electron mobility and the hole mobility are different from each other; therefore, a bias electric field is generated in a self-aligned manner. In the dry etching process, fluorine ions that are accelerated by this bias are irradiated onto the sample to cause chemical reactions in volatile substances, thereby removing the photoresist. Similar to the above example, the bias electric field also causes drifting of the transistor performance and deterioration of breakdown resistance of the gate insulating film, thereby causing plasma damage. Thus, even with the cast film formation method using an organic insulating film, the results are unsatisfactory.
To address the above problems, there is a technology of forming an interlayer insulating film by depositing beforehand an organic insulating film in areas apart from the through-hole, and providing the through-hole by screen printing.
Next, the principle, the performance, and problems of screen printing are described.
a) Principle of Screen Printing
An emulsion is disposed on a stainless mesh with a desired aperture (screen printing plate), and printing ink is transferred from the aperture of the plate to a print object by squeegee action. The printed matter is evened out by leveling the transferred ink (see FIG. 5).
b) Print Pattern and Required Ink Performance
Description for Print Pattern A
An emulsion that blocks ink is disposed in an inverse pattern. A stainless mesh is provided at the emulsion aperture, which hampers the passage of ink. Immediately after the squeegee action, ink is transferred onto the print object in island-like forms. As time passes, the island-like forms of ink are leveled, changing into a planar, continuous film, and forming a pattern. This leveling operation has a detrimental effect in terms of reproducing dimensions of the pattern. Specifically, due to the leveling operation, the resultant print pattern becomes larger than the original dimensions of the aperture in the emulsion.
Description for Print Pattern B
By the same principle, dimensions of the through-hole become small.
Generally, print pattern A and print pattern B are distinguished as a positive type and a negative type, respectively. In conventional screen printing methods, negative type patterns are rarely used.
Screen printing is performed to form structures (thick-film patterns) for electrode printing in rib materials and multilayer ceramic wiring substrates of plasma displays, and internal electrode printing in laminated ceramic condenser components. In these examples, positive type patterns are used.
Negative type pattern printing is occasionally performed to form protective films for a mounting circuit board. In this case, an aperture is formed with dimensions in millimeter order. The positive type patterns have dimensions of 30 μm to 50 μm for mass production, and 10 μm to 30 μm for research stages. In general, the criteria values of stable machining for negative type patterns are 200 μm to 300 μm.
Through-hole dimensions designed for organic TFT array substrates are approximately 150 μm to 5 μm, which are less than or equal to the criteria values of stable machining; although these dimensions may depend on the pixel integration density. Accordingly, screen printing has not been conventionally employed for printing interlayer insulating films, although the method is simple.
c) Problems in Application to Organic TFT
As shown in FIG. 2, the interlayer insulating film 6 is directly laminated on the organic semiconductor layer (the active layer 5 shown in FIG. 1). Thus, the organic solvent included in the interlayer film ink (hereinafter, simply referred to as “paste”) dissolves or swells the organic semiconductor layer, which may result in degraded semiconductor properties. Accordingly, there is a need for a simple method of manufacturing elements in which these problems are solved.
Next, examples of manufacturing an amorphous Si active substrate and an organic semiconductor (pentacene) active substrate are described.
An active substrate using organic semiconductor materials is more advantageous than an active substrate using Si system semiconductor materials employed in flat panel displays. Specifically, the advantages include reductions in manufacturing costs due to simple processes, use of a simple manufacturing device, and product cost reductions accompanied by using the simple device. Today, efforts are being made to develop active substrates using organic semiconductor materials for flat panel displays.
<Example of manufacturing amorphous Si active substrate>    1. Substrate    2. Formation of gate electrode (first electrode)            chromium vacuum film formation, photolithographic etching            3. Formation of gate insulating film (first insulating film)            SiO2 vacuum film formation (sputtering film formation)            4. Formation of active layer            film formation of hydrogenated amorphous Si by plasma CVD (chemical vapor deposition) method and photolithographic etching            5. Formation of source/drain electrodes (second electrode pair)            aluminum vacuum film formation, photolithographic etching            6. Formation of interlayer insulating film (second insulating film)            SiO2 vacuum film formation (sputtering film formation)            7. Open contact hole            photolithographic etching            8. Formation of individual electrode (third electrode)            aluminum vacuum film formation, photolithographic etching        
<Example of manufacturing organic semiconductor (pentacene) active substrate>    1. Substrate    2. Formation of gate electrode (first electrode)            chromium vacuum film formation, photolithographic etching            3. Formation of gate insulating film (first insulating film)            SiO2 vacuum film formation (sputtering film formation)            4. Formation of source/drain electrodes (second electrode pair)            aluminum vacuum film formation, photolithographic etching            5. Formation of active layer            film formation of pentacene by vacuum evaporation and photolithographic etching            6. Formation of interlayer insulating film (second insulating film)            SiO2 vacuum film formation (sputtering film formation)            7. Open contact hole            photolithographic etching            8. Formation of individual electrode (third electrode)            aluminum vacuum film formation, photolithographic etching        
The difference between forming the amorphous Si active substrate and the organic semiconductor (pentacene) active substrate is the method of forming the active layer. The hydrogenated amorphous Si is formed by the plasma CVD method. To obtain a high-quality semiconductor, the substrate temperature needs to be high enough (at 250° C. to 350° C.); therefore, the active substrate is made of glass.
On the other hand, the substrate temperature can be at room temperature in the case of film formation for the pentacene semiconductor; therefore, the active substrate can be made of plastic.
In terms of the manufacturing device, a plasma CVD device is used instead of a vacuum evaporation device; therefore, the cost of the device and running costs are certainly reduced.
Recently, the field of printing electronics has been rapidly growing. Specifically, there is a technology of forming conventional metal wirings by an inkjet method or other printing methods by using conductive polymers or nano-metal ink. There is another technology of forming a pattern for a functional film without performing vacuum film formation; i.e., making ink from an organic semiconductor material other than pentacene such as a polymer, by dissolving it in a solvent.
For example, organic semiconductor materials such as polythiophene and fluorene-thiophene copolymer are used in these technologies.
When a fluorene-thiophene copolymer (F8T2) is formed by the inkjet method in the example of manufacturing an organic semiconductor (pentacene) active substrate described above, an even more simple process can be performed at step 5 instead of vacuum evaporation and photolithographic etching. It is also possible to make ink from polyethylene-dioxy-thiophene (PEDOT) to obtain a conductive polymer to be used for wiring, or to use nano-silver ink for an inkjet coating and applying heat treatment of 200° C. to be used for wiring.
These printing electronics technologies can substitute for the vacuum film formation and photolithographic etching processes performed in forming electrodes at steps 1, 2, and 3; therefore, simplification of processes and devices can be promoted significantly.
When the inkjet method is employed for forming a wiring pattern, the dimensions of the pattern are restricted by the volume of ejected ink and landing accuracy of ink. Presently, wirings of 100 microns can be formed; however, improvements need to be made to form even more microscopic wirings.
The inventors of the present invention have succeeded in forming a pattern having intervals of 5 μm for a second electrode layer of a transistor by using the inkjet coating method. Specifically, the pattern is formed by simple processes including changing the surface energy of the base, and applying light treatment on surfaces that easily absorb ink and surfaces that do not easily absorb ink; and by a self-eliminating mechanism of the coated ink (see Patent Document 3). It is imperative to form a pattern with microscopic intervals for the second electrode of the transistor in order to enhance performance of the transistor. Further, an application of a wiring technology employing the inkjet method has been submitted with Patent Document 4.
An organic transistor active substrate according to an embodiment of the present invention includes the organic transistor having a structure as shown in FIG. 2, on which the through-hole 7, the interlayer insulating film 6, and the individual electrode 8 are two-dimensionally disposed. The organic transistor active substrate transmits image signals from a source electrode of the organic transistor to the individual electrode (pixel electrode 8) via the through-hole 7.
FIG. 3 is a top view of the organic transistor active substrate. The organic transistor active substrate includes a gate electrode 302, a drain electrode 304, a source electrode 305, a signal line 308, a scanning line 309, and a pixel electrode 310 (corresponding to the individual electrode 8 shown in FIG. 2).
An electrophoretic display according to an embodiment of the present invention has a structure as shown in FIG. 4, in which the electrophoretic microcapsules 9 are enclosed in between the individual electrode 8 and the transparent electrode 10 supported by the supporting substrate 11. The electrophoretic display displays black/white according to image signals received by the individual electrode 8 of the organic transistor. The structure shown in FIG. 4 is used for one pixel.
The manufacturing method using the conventional printing technology of the organic transistor shown in FIG. 1 can be significantly simplified as follows (the arrow → indicates the improvement).    1. Substrate    2. Formation of gate electrode (first electrode)            chromium vacuum film formation, photolithographic etching        → formation by nano-silver ink/IJ (inkjet) method        (vacuum film formation, photolithographic etching are not performed)            3. Formation of gate insulating film (first insulating film)            SiO2 vacuum film formation (sputtering film formation)        → formation of polyimide by spin coating        (vacuum film formation is not performed)            4. Formation of source/drain electrodes (second electrode pair)            aluminum vacuum film formation, photolithographic etching        → formation by partial surface modification of polyimide by light irradiation+nano-silver ink/IJ method        (vacuum film formation, photolithographic etching are not performed to form resist pattern for processing)            5. Formation of active layer            film formation of pentacene by vacuum evaporation, and photolithographic etching        → formation with polymer organic semiconductor material by IJ method (vacuum film formation, photolithographic etching are not performed)        
With this simplified method, costs can be significantly reduced.
However, the conventional method is performed in subsequent processes to form the interlayer insulating film (second insulating film) 6, to open the contact hole, and to form the individual electrode 8 shown in FIG. 2; therefore, costs are not thoroughly reduced.
A preferable printing method for manufacturing an active substrate made of organic TFT is described below.
To form a first electrode layer (gate electrode), a method of printing a pattern of less than or equal to 100 μm is selected. Examples of such a method include inkjet printing, intaglio printing, and relief printing. A second feature required in the electrode layer formation is to form a thin electrode film.
The transistor is formed by laminating a functional film, and the resulting laminated pattern needs to be prevented from being cut off due to a difference in levels with the base. In intaglio printing, it is possible to print patterns with line widths of 20 μm, so that the resolution is sufficient; however, intaglio printing is inappropriate for forming thin films (the film thickness is generally 2 to 3 μm in intaglio printing).
Another property required in a printing method for the electrode layer formation is that the printing ink type is not restricted. An electrode is formed by printing with nano-metal ink, and the electrode is heat treated so as to provide conductivity. An intaglio printing material, which does not degrade properties of nano-metal ink, is now being developed. On the other hand, any type of ink can be used with the inkjet method as long as the viscosity and the surface tension are matched. It is preferable to use the same manufacturing device for forming the source/drain electrodes to be described later, because the inconvenience of using plural devices and managing plural manufacturing methods can be eliminated, and capital investment costs can be reduced.
Properties required for a printing method for forming a second electrode layer (source/drain electrodes) are as follows: a space of less than or equal to 20 μm can be resolved, and the positional shift with respect to the base pattern needs to be less than or equal to 3 μm. The aforementioned intaglio printing and relief printing methods do not satisfy the requirement of positional alignment. The inventors of the present invention have proposed an IJ printing method employing a technology for controlling wettability of polyimide by light irradiation (Japanese Laid-Open Patent Application No. 2006-060079).
The IJ method is preferable for printing on organic semiconductor material, because any ink type can be applied, and is also advantageous in that the same manufacturing device can also be used for forming the source/drain electrodes.
Properties required for a printing method for forming an interlayer insulating film are described below. The pixel electrode is disposed on the interlayer insulating film; therefore, sufficient electrical insulating properties need to be realized, and the interlayer insulating film needs to be adequately isolated dielectrically. The reason is that when the pixel electrode is provided with electric potential, the interlayer insulating film serves as a dielectric film and provides a dielectric field to the base organic semiconductor layer. This may cause the operating point of the transistor to shift. In order to solve such a problem, the interlayer insulating film needs to have a thickness of several μm.
A through-hole needs to be formed through the interlayer insulating film having a thickness of several μm, in order to make electric connection with the base electrode. Accordingly, the interlayer insulating film is to be printed beforehand in parts apart from the electrical connection. With the intaglio printing method, thick films can be formed; however the printing positions cannot be sufficiently aligned with respect to the base pattern. On the other hand, these disadvantages can be solved with the screen printing method.
When forming pixel electrodes, an electrical disconnection at the through-hole is prevented by printing the film with a thickness corresponding to concavities and convexities of the printing base. This requires a printing method in which positional alignment is highly precise and thick films can be formed; accordingly, the screen printing method is selected. Screen printing is also employed for forming interlayer insulating films, and is therefore advantageous in that a common device can be used and manufacturing methods are conveniently managed.